1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device which includes an N-channel type low-voltage MOS transistor and an N-channel type high-voltage MOS transistor.
2. Description of the Related Art
In a semiconductor integrated circuit a low-voltage element and a high-voltage element are both used, depending on the respective use thereof. For example, a high-voltage element is used only in a section which directly handles a voltage applied to and sent from the semiconductor integrated circuit, while a low-voltage element is used in a section which performs internal signal processing. The low-voltage element occupies a smaller area than the high-voltage element. Accordingly, the use of the high-voltage element only in a section which determines the performance specification of the integrated circuit and is difficult to modify, such as a section relating to voltages exchanged with outside, and the use of the low-voltage element in a section for performing the internal processing permit the reduction in the area of the semiconductor integrated circuit and the manufacturing cost thereof.
FIG. 2 is a schematic plan view of the above-mentioned low-voltage MOS transistor and the high-voltage MOS transistor formed on the same substrate and in the same semiconductor integrated circuit.
The low-voltage N-channel MOS transistor (hereinafter, referred to as NMOS) 101 includes a gate insulating film 8, a gate electrode 9 disposed directly above the gate insulating film 8, and a source/drain region provided on both ends thereof. The source/drain region includes the first N-type high impurity concentration region 2 of low resistance for contacting metal, and the first N-type low impurity concentration region 3 for alleviating electric field intensity.
In this case, the first high concentration N-type region 2 in particular is doped with atoms of, for example, arsenic or antimony, which has a small diffusion coefficient and whose thermal diffusion is small. The reason for this is to avoid diffusion of the high impurity concentration in a lateral direction due to the heat treatment process performed during the semiconductor processing as much as possible, adversely resulting in reduction in length of the first N-type low impurity concentration region 3. The problem can be avoided by securing a predetermined length for the first N-type low impurity concentration region 3 if the first N-type low impurity concentration region 3 is designed to have an ample length so as to allow for the diffusion, which leads to, however, an increase in an area to be occupied by the element to thereby increase cost.
Meanwhile, the high-voltage NMOS 102 includes the gate insulating film 8, the gate electrode 9 disposed directly above the gate insulating film 8, and a source/drain region provided on both ends thereof. The source/drain region includes the second N-type high impurity concentration region 4 and a second N-type low impurity concentration region 5, and the high-voltage NMOS 102 further includes an oxide film 10 formed on the second N-type low impurity concentration region 5, the oxide film 10 being thicker than the gate insulating film 8. The thick oxide film 10 has an effect of alleviating the gate-drain electric field intensity. The above-mentioned drain structure is adapted to a case where the drain needs to be resistant to a voltage of 20 V or more, and a withstanding voltage is adjusted by varying the length and the concentration of the N-type low impurity concentration region of the drain. Further, in a case where the gate of the high-voltage NMOS 102 is also applied with a voltage which is larger than the voltage applied to the low-voltage NMOS 101, the thickness of the gate insulating film 8 may be increased only for the portion corresponding to the high-voltage NMOS 102 according to the voltage.
The second N-type high impurity concentration region 4 of the high-voltage NMOS 102 is generally formed through the same process for forming the N-type highly-concentrated impurity region 2 of the low-voltage NMOS 101 for the purpose of reducing process cost, and arsenic or antimony is used as the impurity to be implanted therein.
Also, the second low impurity concentration region 4 is often used in combination with a channel stop structure provided outside of the element region, thereby reducing process cost. The second low impurity concentration region 4 accordingly has an oxide film obtained through the LOCOS process disposed thereon, and the concentration of the second low impurity concentration region 4 is adjusted to a value that is not inverted due to the wiring. In general, in a case where the high-voltage NMOS is less frequently used in the semiconductor integrated circuit, limitations are imposed on the high-voltage NMOS in terms of structure for reducing cost as described above, and the element has to be designed under the limiting conditions.
Further, there may be provided a third N-type low impurity concentration region 7 to the depth of several μm on the drain side of the high-voltage NMOS 102, in such a manner that the third N-type low impurity concentration region 7 covers the entire N-type high impurity concentration region 4 and a part of the N-type low impurity concentration region 5. The third N-type low impurity concentration region 7 is provided so as to complement a small contact area between the N-type low impurity concentration region 5 and the N-type high impurity concentration region 4 on the drain side shown in FIG. 3A, which produces an effect of preventing a thermal destruction from being caused by a high electric field and a large current to be applied when the high-voltage NMOS 102 electrically operates. The thermal destruction phenomenon described above not only results in an instant destruction but also affects the long-term reliability.
In order to form the N-type low impurity concentration region 7, the region needs to be doped with an impurity, such as phosphorus, which has a high diffusion coefficient and is easy to thermally diffuse, and also needs to be subjected to high-heat processing with a temperature of 1,000° C. or more in order to attain a certain predetermined diffusion depth.
The above-mentioned structure of the high-voltage NMOS is disclosed in JP 06-350084 A and in JP 3270405 B.
In the conventional high-voltage NMOS, it is necessary to provide a deep N-type impurity region covering the entire N-type high impurity concentration region and a part of the N-type low impurity concentration region, and the formation of the region additionally involves a heat treatment process, which results in the limitation of the performance of the element, and a photolithography process, which leads to an increase in cost. On the other hand, if the deep N-type impurity region is not provided, there has been a problem that a breakdown withstanding voltage is not sufficiently attained and a long-term reliability is impaired.